1. Field of the Invention
This invention relates to an electronic display and more particularly to a liquid crystal display and a storage cell configured within the display for storing and buffering video data therein.
2. Background of the Relevant Art
Liquid crystal displays (LCDs) have become a very popular form of electronic display and are well known. LCDs operate as light modifiers or light valves. As such LCDs are not self-illuminating but instead, operate by modifying ambient incoherent light supplied by an external source such as the sun, a table lamp or other room light sources. A conventional LCD comprises a liquid crystal medium hermetically sealed between a pair of glass plates. On the outer surface of each glass plate is a polarizing filter, wherein the filter on one glass plate may be capable of polarizing light at a different angle than the filter on the other glass plate. If electrodes on the inner surface of each glass plate are subject to a voltage differential, a resulting electric field perpendicular through the liquid crystal plane can re-orient the molecules. For example, during times in which an electric field is not present, polarized light from one filter can be aligned with the other filter to allow light to pass completely through the LCD. Conversely, during times in which an electric field is present, the molecules will orient themselves such that the polarized light from one filter will be blocked by the other filter. The orientation of liquid crystal molecules in the presence of an electric field is well known and may be described as dynamic scattering or twisted nematic (TN) phenomena.
Turning now to the block diagram of FIG. 1, LCD 10 can receive video data and be addressed via VGA controller 12. VGA controller 12 can provide direct interface to an I.B.M..RTM.-compatible AT, XT or PS bus 14. A suitable VGA controller 12 can be obtained from Cirrus Logic, Inc., Fremont, Calif., part no. CL-GD6410. VGA controller not only provides direct interface to host 16 via bus 14, but also synchronizes refresh and clocking operations between bus 14 and LCD 10 via clock sync. 18 of common design.
Video information is generally transmitted over buses 14, 22 and 24, and between LCD 10 and a video dynamic access memory (DRAM) 20. VGA controller 12 operates to address and to read and write video data to and from DRAM 20. DRAM 20 is addressed and the appropriate data signal transmitted according to conventional memory addressing techniques, whereby the resulting data is sent to a select pixel within LCD 10. DRAM 20 is typically placed within or near host computer 16 and is separate or remote from LCD 10. Host 16 transmits video information over bus 14 to VGA controller 12 for writing into video DRAM 20. VGA controller 12 handles all host 16 read and write accesses to DRAM 20. VGA controller 12 associates with each pixel of LCD 10 a corresponding region of DRAM 20. The VGA controller 12 maintains an image on LCD 10 by continuous refresh, wherein, in an iterative and sequential fashion, regions of DRAM 20 are read and sent to the corresponding pixel of LCD 10 across bus 24. This refresh operation consumes a substantial portion of the bandwidth of DRAM 20 and its associated bus 22. Host 16 performs read and write accesses to DRAM 20 to effect drawing operations. By changing a region in DRAM 20, the corresponding pixel on LCD 10 will be affected. It is desirable to maintain a large bandwidth of host 16 accesses into DRAM 20 in order to provide for high performance drawing operations. This is in direct competition with the fixed and large bandwidth requirement for LCD 10 refresh.
Turning now to FIG. 2, an exploded view of LCD 10 according to a prior design is shown. LCD 10 includes a pair of glass plates or panels 22 and 24, and on the outer surface of each glass panel is a polarizer filter. Polarizer filter associated with panel 22 is denoted as reference numeral 26 and polarizer filter associated with panel 24 is denoted as reference numeral 28. On the inside surface of glass panel 22 is a common electrode 30, often called the "backplane" of the LCD. On the inside surface of glass panel 24 is a lithography-produced topography comprising a matrix or grid of orthogonally placed conductors, active devices and separate electrodes, the separate electrodes are often called "display electrodes." The conductors are used to carry video data and addressing signals sent to and from VGA controller 12. Specifically, electrodes which receive video data are designated as bit lines 32, wherein the bit lines are spaced parallel from each other. Video data on one bit line can be read into or written from a select display electrode 36 by a word line 34 spaced parallel to other word lines 34 and substantially perpendicular to each bit line 32. Word lines 34 are thereby used to randomly address a select display electrode 36 with video data contained within a respective bit line 32. The addressing scheme and methodology is well known and generally follows standard DRAM multiplexing techniques. Placed adjacent each display electrode 36 within the matrix is a pass-gate transistor 38 which, depending upon the voltage state upon its gate terminal, transmits bit line video data to and from electrode 36. Additional details regarding the layout and connection configuration between bit line 32, word line 34, display electrode 36, and pass-gate transistor 38 are provided hereinbelow.
Placed over the inside surface topography of conductors 32 and 34, over transistors 38, and over display electrodes 36 is a dielectric layer (not shown) of sufficient insulative quality to electrically isolate bit lines 32, word lines 34 and transistors 38 from each other and from an adjacent liquid crystal medium 40. When brought together, liquid crystal medium 40 is in contact with the dielectric material and is in electric field contact with the display electrodes 36 which are voided by standard etching techniques of dielectric material immediately thereabove. It is understood that alignment coatings and/or passivation coatings (not shown) are generally placed between electrode 30 and liquid crystal medium 40 as well as between each display electrode 36 and liquid crystal medium 40 to ensure current flow will not occur through the medium and that only electric field will be selectively present.
LCDs operate by either permitting the transferral of light between the glass panels or by blocking the light at select regions, often called "pixel" regions generally represented by the geometric size of individual display electrodes 38. Incoherence, ambient light 42 can be transmitted or reflected into one surface of LCD 10 allowing filter 28 to polarize light 42 to a coherent, linearly polarized state. The polarized light can either be re-aligned such that it passes through second filter or, if electric field is present, the light can be blocked by the second filter. Accordingly, sections of light or pixel regions can present themselves as relatively light or relatively dark areas necessary for visual contrast detection.
Referring now to FIG. 3, a partial circuit schematic of LCD 10 of a prior design is shown. One cell within a plurality of cells (or matrix) is shown having display electrodes 36 connected to the source-drain path of pass-gate transistors 38. Pass-gate transistors are activated by an appropriate voltage level upon its gate. Pass-gate transistors are manufactured upon glass panel 24 according to standard semiconductor processing and may be configured as thin film, n-channel, enhancement-type MOSFETs. Once the voltage upon word line 34 exceeds a threshold amount, pass-gate transistor 38 allows video data within respective bit line 32 to pass through the source-drain path and onto display electrode 36. Common electrode 30 provides a uniform voltage state upon one side of liquid crystal media 40 such that electric field selectivity is entirely controlled by the voltage state of respective display electrodes 36 and its associated bit line 32 voltage.
Referring now to FIG. 4, a two-dimensional view of an active matrix addressing scheme of a typical prior design is shown. The active matrix receives video data from the remote DRAM and presents the data as input signals (DI) to buffer 44. Buffer 44 must generally present significant current drive in order for the attached bit line to refresh an entire row or column of display electrodes. Large amounts of current driven through the elongated bit line can oftentimes become capacitively coupled to overlying word lines which are separated by a fairly thin layer of dielectric material described above. Capacitive coupling between bit and word lines is dramatically increased whenever the current associated with those lines is significant. Further, the very small distances which separate the bit and word lines make capacitive coupling between those lines a major problem. Capacitive coupling to an overlying word line may partially activate a cell which should not be active. Partial activation will appear to reduce the contrast of the cells which are targeted to be on. The resulting contrast-reducing phenomena is often referred to as "ghosting." To overcome ghosting, the dielectric material must be made thicker at the location between the bit and word lines or, the current transmitted through the respective bit and word lines must be reduced. It is not recommended, however, that the dielectric material be increased in thickness since any increase in cell thickness can reduce the visual angle, or viewing angle of the LCD. Factors such as viewing angle and contrast are critical to satisfactory LCD performance. As viewing angle decreases, so does the contrast. The rate of decrease of contrast in relation to viewing angle is a function of the ratio of the smallest dimension of the display electrode or cell to its thickness. If thickness is increased only slightly, the viewing angle and contrast will inversely decrease.
Another problem associated with large drive or buffered currents placed within elongated bit and/or word lines extending across the panel is the need for larger current-carrying conductors. Conductors of larger diameter are necessary to handle the drive currents and, as such, the larger diameter conductors will require larger surface real estate thereby taking away from the area available for display electrodes 36. The result being smaller display electrodes and larger spacing between electrodes. Smaller display electrodes thereby presents a smaller pixel area and reduced image contrast and clarity at the object or image edge.
A still further problem associated with large drive currents within bit and/or word lines is that which is commonly referred to as "smearing." A large current presented upon the word lines or bit lines presented to a column or row of pass-gate transistors may force the respective transistors into a saturation region. A saturated pass-gate transistor may not quickly turn off at the desired moment, causing a "smeared" object or image to appear as it moves across the screen. Although thin film transistors with low thresholds operating in the linear region generally avoid this problem, the transistors nevertheless can be inadvertently overdriven by large buffer outputs connected to elongated bit lines and associated source terminals.